In a system which includes a processor which executes bus cycles on a bus and in which a signal is sent back to the processor indicative of completion of a bus cycle, completion of the cycle is suspended and then restarted by storing the address, deasserting control signals, isolating the processor from...http://www.google.fr/patents/US5150467?utm_source=gb-gplus-shareBrevet US5150467 - Method and apparatus for suspending and restarting a bus cycle
Method and apparatus for suspending and restarting a bus cycle
