One or more columns of multi-function tiles are positioned between CLB tiles of the FPGA array. Each multi-function tile includes multiple function elements that share routing resources. In one embodiment, a multi-function tile includes a configurable, dual-ported RAM and a multiplier that share routing...http://www.google.fr/patents/US6573749?utm_source=gb-gplus-shareBrevet US6573749 - Method and apparatus for incorporating a multiplier into an FPGA
Method and apparatus for incorporating a multiplier into an FPGA
