A nonvolatile memory integrated circuit arrayed in rows and columns is disclosed. Parallel lines of implant N-type regions are formed in a P-well of a semiconductor substrate, with lines of oxide material isolating each pair of the lines. Columns of memory cells straddle respective pairs of the implant...http://www.google.fr/patents/US7633114?utm_source=gb-gplus-shareBrevet US7633114 - Non-volatile memory integrated circuit
