In a disk control device arranged to include a CPU, a plurality of channel control units, a plurality of disk control units, a cache memory, and a data transfer integrated circuit communicably connected to the cache memory via a plurality of data buses, when receiving a request for access to the cache...http://www.google.fr/patents/US7003637?utm_source=gb-gplus-shareBrevet US7003637 - Disk array device with utilization of a dual-bus architecture dependent on data length of cache access requests
Disk array device with utilization of a dual-bus architecture dependent on ...
