A microprocessor is provided including a pair of caches and a dependency checking structure for accesses between the pair of caches. One of the pair of caches is accessed from the decode stage of the instruction processing pipeline, while the other is accessed from the execute stage. The...http://www.google.fr/patents/US5813033?utm_source=gb-gplus-shareBrevet US5813033 - Superscalar microprocessor including a cache configured to detect dependencies between accesses to the cache and another cache
Superscalar microprocessor including a cache configured to detect ...
