A system and method for applying a stress to a hierarchical memory structure in parallel, testing the memory structure for weak defects. The system and method includes writing a logic 0 into all the memory cells in a memory structure. All the high address predecoded lines and alternating predecoded lines...http://www.google.fr/patents/US6909648?utm_source=gb-gplus-shareBrevet US6909648 - Burn in system and method for improved memory reliability
Burn in system and method for improved memory reliability
