A memory array employing shared bit-lines. A memory is formed from an array of plural bit-cells organized as plural columns and plural rows. Plural word-lines are aligned with each for the rows, and each is electrically coupled to a discrete fraction of the bit-cells its corresponding row. The memory...http://www.google.fr/patents/US7092279?utm_source=gb-gplus-shareBrevet US7092279 - Shared bit line memory device and method
