A multiple processor network is described whereby a "Sender" processor can address a "Receiver" processor within a system of processors and select the first processor which is found to be in an idle condition, and whereby a Sender can address processors of a specially indicated type. A Global Memory...http://www.google.fr/patents/US4245306?utm_source=gb-gplus-shareBrevet US4245306 - Selection of addressed processor in a multi-processor network
Selection of addressed processor in a multi-processor network
