A memory controller provides a series of queues between the processor and the PCI bus and the memory system. Memory coherency is maintained in two different ways. Before any read operations are accepted from the PCI bus, both of the posting queues must be empty. A content addressable memory (CAM)...http://www.google.fr/patents/US5819105?utm_source=gb-gplus-shareBrevet US5819105 - System in which processor interface snoops first and second level caches in parallel with a memory access by a bus mastering device
System in which processor interface snoops first and second level caches in ...
