A system for operation verification of a semiconductor integrated circuit has a central processing unit, a design layout memory unit storing design layout information including the design layout configuration of the semiconductor integrated circuit, and a predicted final layout memory storing a predicted...http://www.google.fr/patents/US7171640?utm_source=gb-gplus-shareBrevet US7171640 - System and method for operation verification of semiconductor integrated circuit
System and method for operation verification of semiconductor integrated circuit
