A two transistor cell NOR architecture flash memory is provided wherein the floating gate transistor is couple between the selection transistor and an associated bit line. The flash memory is deposited within a triple well and operates according to a Fowler-Nordheim tunnel mechanism. Programming of memory...http://www.google.fr/patents/US6307781?utm_source=gb-gplus-shareBrevet US6307781 - Two transistor flash memory cell
