A system and method for generating design constraints for a logic synthesized block from timing analysis of the block. A timing analysis of logic described in software is performed for each of various operating modes of a circuit in which the logic is used. Timing data is extracted from the timing analysis...http://www.google.fr/patents/US6185518?utm_source=gb-gplus-shareBrevet US6185518 - Method and system for logic design constraint generation
Method and system for logic design constraint generation
