A boundary scan test circuit comprises a plurality of register cells correspondingly to external pins of a semiconductor device, the register cells being coupled together to form a shift register during a test operation mode. The register cells includes a first selector for selecting one of a parallel...http://www.google.fr/patents/US5477493?utm_source=gb-gplus-shareBrevet US5477493 - Semiconductor device having a boundary scan test circuit
Semiconductor device having a boundary scan test circuit
