Disclosed is a semiconductor memory (18, 20, 100, 200) having a hierarchical bit line architecture including local bit lines (LBL.sub.1, LBL.sub.2) on a lower fabrication layer, coupled to memory cells (MC), and master bit lines (MBL) on a higher fabrication layer, each coupled to an associated sense...http://www.google.fr/patents/US5966315?utm_source=gb-gplus-shareBrevet US5966315 - Semiconductor memory having hierarchical bit line architecture with non-uniform local bit lines
Semiconductor memory having hierarchical bit line architecture with non ...
