A method for manufacturing a three-dimensionally structured vertical transistor or memory cell forms a silicon-on-insulator (SOI) structure on a semiconductor substrate and sequentially deposits a drain region, a channel region and a source region on the SOI substrate structure. The transistor includes...http://www.google.fr/patents/US6018176?utm_source=gb-gplus-shareBrevet US6018176 - Vertical transistor and memory cell
