A method for storing data in a generally-diagonal pattern in blocks of a flash EEPROM array by which the least number of memory cells are affected by a failure of either a row conductor or a column conductor, and apparatus for addressing the flash array to produce such a generally-diagonal storage pattern....http://www.google.fr/patents/US5490264?utm_source=gb-gplus-shareBrevet US5490264 - Generally-diagonal mapping of address space for row/column organizer memories
Generally-diagonal mapping of address space for row/column organizer memories
