Memory control that access memory devices having different read latencies is described. In on embodiment, a memory controller may include read latency logic to identify and match received read data with read commands to the memory devices based on values indicative of the read latency for the memory...http://www.google.fr/patents/US20070005922?utm_source=gb-gplus-shareBrevet US20070005922 - Fully buffered DIMM variable read latency
