A system is provided for ensuring that a ethernet controller operates to optimize bus latency and central processing unit (CPU) utilization in a network environment when reviewing data packets. Through the efficient use of a plurality of buffer memories and a driver, the bus utilization in conjunction...http://www.google.fr/patents/US5533203?utm_source=gb-gplus-shareBrevet US5533203 - Start of packet receive interrupt for ethernet controller
Start of packet receive interrupt for ethernet controller
