An apparatus and method for accelerating interpreters, interpretive environments, may manage pinning of a processor cache closest to a processor. An instruction set implementing a virtual machine may store each instruction in a single cache line as a compiled, linked loaded image. After loading, the...http://www.google.fr/patents/US6470424?utm_source=gb-gplus-shareBrevet US6470424 - Pin management of accelerator for interpretive environments
Pin management of accelerator for interpretive environments
