A tileable structure is provided for logic array devices. The tileable structure has a mirror-symmetrical arrangement of sets of logic blocks, common control sections for the logic block sets, surrounding interconnect lines, and switching areas at intersections of the interconnect lines....http://www.google.fr/patents/US6154051?utm_source=gb-gplus-shareBrevet US6154051 - Tileable and compact layout for super variable grain blocks within FPGA device
Tileable and compact layout for super variable grain blocks within FPGA device
