A memory circuit including at least one array of flash memory cells organized into one or more physically separate decode blocks and a controller which monitors the disturb effect on each independently erasable "erase" block of cells of each decode block due to erasures of other erase blocks in the same...http://www.google.fr/patents/US5920501?utm_source=gb-gplus-shareBrevet US5920501 - Flash memory system and method for monitoring the disturb effect on memory cell blocks due to high voltage conditions of other memory cell blocks
Flash memory system and method for monitoring the disturb effect on memory ...
