A circuit for buffering and parity checking digital data communicated between first and second data buses includes a plurality of bidirectional bit buffer circuits. Each of the bidirectional bit buffer circuits includes: a first data path comprising a data receiver, latch, and driver connected in series...http://www.google.fr/patents/US5107507?utm_source=gb-gplus-shareBrevet US5107507 - Bidirectional buffer with latch and parity capability
Bidirectional buffer with latch and parity capability
