A method and apparatus for synchronizing a plurality of processors. Each processor runs off of its own independent clock, indicates the occurrence of a prescribed process or event on one line and receives signals on another line for initiating a processor wait state. Each processor has a counter which...http://www.google.fr/patents/US5353436?utm_source=gb-gplus-shareBrevet US5353436 - Method and apparatus for synchronizing a plurality of processors
Method and apparatus for synchronizing a plurality of processors
