In a semiconductor memory for reading and writing of stored charge in an X-Y address system by arranging a plurality of memory cells each including a capacitance element and one MOS-FET in matrix, this invention discloses a semiconductor memory using multiple level storage structure for read and write...http://www.google.fr/patents/US4709350?utm_source=gb-gplus-shareBrevet US4709350 - Semiconductor memory using multiple level storage structure
Semiconductor memory using multiple level storage structure
