A system (10) translates memory addresses. Processing circuitry (12) provides an effective address to a storage array (14, 16) having a plurality of stored effective addresses, each of the plurality of stored effective addresses having a corresponding pair of a lock bit and a valid bit. An output tag...http://www.google.fr/patents/US7185170?utm_source=gb-gplus-shareBrevet US7185170 - Data processing system having translation lookaside buffer valid bits with lock and method therefor
Data processing system having translation lookaside buffer valid bits with ...
