An on-chip checking and correction circuit extends the program/erase endurance of a semi-conductor memory array and catches data retention failures in individual memory cells of the array. For each data byte in the memory array, four parity bits are computed using a modified Hamming Code and stored in...http://www.google.fr/patents/US4612640?utm_source=gb-gplus-shareBrevet US4612640 - Error checking and correction circuitry for use with an electrically-programmable and electrically-erasable memory array
Error checking and correction circuitry for use with an electrically ...
