A method is disclosed for forming a split-gate flash memory cell where the floating gate of the cell is self-aligned to a shallow trench isolation (STI), which in turn makes it self-aligned to source and to word line. This will advantageously affect a shrinkage in the size of the memory cell. In a first...http://www.google.fr/patents/US6403494?utm_source=gb-gplus-shareBrevet US6403494 - Method of forming a floating gate self-aligned to STI on EEPROM
Method of forming a floating gate self-aligned to STI on EEPROM
