A cycle steal mechanism for enabling a host processor to initiate and control the cycle stealing of data to or from a storage unit located in an I/O controller which is connected to the I/O channel bus of the host processor. The I/O controller also includes a microprocessor and a direct memory access...http://www.google.fr/patents/US4417304?utm_source=gb-gplus-shareBrevet US4417304 - Synchronous cycle steal mechanism for transferring data between a processor storage unit and a separate data handling unit
Synchronous cycle steal mechanism for transferring data between a processor ...
