A first P channel transistor and a first N channel transistor are defined by first and second gate electrodes, respectively. The second gate electrode is electrically connected to the first gate electrode. A second P channel transistor and a second N channel transistor are defined by third and fourth...http://www.google.fr/patents/US20090224317?utm_source=gb-gplus-shareBrevet US20090224317 - Cross-Coupled Transistor Layouts in Restricted Gate Level Layout Architecture
Cross-Coupled Transistor Layouts in Restricted Gate Level Layout Architecture
Numéro de demande: 12/402,465 Numéro de publication: US 2009/0224317 A1 Date de dépôt: 11 mars 2009 Brevet délivré: US7956421 ( Date de délivrance 7 juin 2011)
