A memory device including segmented bit lines with memory cells coupled to a data cache is provided. A segmented bit line includes a bias transistor to selectively connect the bit line to a source line. Further, a physical implementation showing a segmentation pattern of the memory device is also pr...http://www.google.fr/patents/US7532509?utm_source=gb-gplus-shareBrevet US7532509 - Segmented bit line for flash memory
