A method of manufacturing a semiconductor device with reduced shallow trench isolation defects and stress is disclosed. The disclosed method begins by providing a silicon substrate including a capping layer. A plurality of isolation trenches are then etched through the capping layer and into the silicon...http://www.google.fr/patents/US6309942?utm_source=gb-gplus-shareBrevet US6309942 - STI punch-through defects and stress reduction by high temperature oxide reflow process
STI punch-through defects and stress reduction by high temperature oxide ...
