The invention provides a decode unit for decoding instructions in a processor. The decode unit comprises opcode decoding logic, operand decoding logic, and a sixteen-bit input. The opcode decoding logic is operable to determine an opcode using five bits of the input and the operand decoding logic is...http://www.google.fr/patents/US7676653?utm_source=gb-gplus-shareBrevet US7676653 - Compact instruction set encoding
