A configurable SRAM for a field programmable gate array. Two memory arrays each have a data input, a data output, a write enable input and port A and B address inputs. First and second address buses are selectively coupled to the port A and port B address inputs through multiplexers such that different...http://www.google.fr/patents/US5883852?utm_source=gb-gplus-shareBrevet US5883852 - Configurable SRAM for field programmable gate array
Configurable SRAM for field programmable gate array
