A memory having gate structures adjacent opposing sidewalls of a semiconductor structure including a channel region and a plurality of charge storage locations between the gate structures and the opposing sidewalls. The channel region is located between two current terminal regions, which in one example...http://www.google.fr/patents/US6903967?utm_source=gb-gplus-shareBrevet US6903967 - Memory with charge storage locations and adjacent gate structures
Memory with charge storage locations and adjacent gate structures
