A read-only-memory cell arrangement comprises memory cells, each having a vertical MOS transistor, in a substrate (21) made of semiconductor material, the various logic values (zero, one) being implemented by gate dielectrics (27, 28) of different thickness. The memory cell arrangement can preferably...http://www.google.fr/patents/US5973373?utm_source=gb-gplus-shareBrevet US5973373 - Read-only-memory cell arrangement using vertical MOS transistors and gate dielectrics of different thicknesses and method for its production
Read-only-memory cell arrangement using vertical MOS transistors and gate ...
