A buffer amplifier architecture for buffering signals which are supplied in parallel to identical chips, particularly DRAM chips, on a semiconductor memory module, is disclosed. The architecture has adjustable delay circuits in each signal line and a delay detector circuit which receives a clock signal...http://www.google.fr/patents/US20040202027?utm_source=gb-gplus-shareBrevet US20040202027 - Buffer amplifier architecture for semiconductor memory circuits
Buffer amplifier architecture for semiconductor memory circuits
Numéro de demande: 10/759,103 Numéro de publication: US 2004/0202027 A1 Date de dépôt: 20 janv. 2004 Brevet délivré: US6894933 ( Date de délivrance 17 mai 2005)
