Cache memory includes a dual or two part cache with one part of the cache being primarily designated for instruction data while the other is primarily designated for operand data, but not exclusively. For a maximum speed of operation, the two parts of the cache are equal in capacity. The two parts of...http://www.google.fr/patents/US4527238?utm_source=gb-gplus-shareBrevet US4527238 - Cache with independent addressable data and directory arrays
Cache with independent addressable data and directory arrays
