This invention includes a capacitorless one transistor DRAM cell that includes a pair of spaced source/drain regions received within semiconductive material. An electrically floating body region is disposed between the source/drain regions within the semiconductive material. A first gate spaced is apart...http://www.google.fr/patents/US20080012056?utm_source=gb-gplus-shareBrevet US20080012056 - CAPACITORLESS ONE TRANSISTOR DRAM CELL, INTEGRATED CIRCUITRY COMPRISING AN ARRAY OF CAPACITORLESS ONE TRANSISTOR DRAM CELLS, AND METHOD OF FORMING LINES OF CAPACITORLESS ONE TRANSISTOR DRAM CELLS
CAPACITORLESS ONE TRANSISTOR DRAM CELL, INTEGRATED CIRCUITRY COMPRISING AN ...
Numéro de demande: 11/488,384 Numéro de publication: US 2008/0012056 A1 Date de dépôt: 17 juil. 2006 Brevet délivré: US7602001 ( Date de délivrance 13 oct. 2009)
