A logic circuit operates write receivers in a dynamic random access memory device in either a low-power mode, high write latency mode or a high-power mode, low write latency mode. The logic circuit receives a first signal indicative of whether the high-power, low write latency mode has been enabled,...http://www.google.fr/patents/US20060152983?utm_source=gb-gplus-shareBrevet US20060152983 - Memory device and method having low-power, high write latency mode and high-power, low write latency mode and/or independently selectable write latency
Memory device and method having low-power, high write latency mode and high ...
Numéro de demande: 11/367,468 Numéro de publication: US 2006/0152983 A1 Date de dépôt: 3 mars 2006 Brevet délivré: US7254067 ( Date de délivrance 7 août 2007)
