An integrated circuit, having a method therefor, includes a memory including a plurality of memory lines, each memory line including a plurality of data cells each to store a data bit, and a plurality of error-correction (EC) cells each to store an EC bit corresponding to the data bits stored in the...http://www.google.fr/patents/US6988237?utm_source=gb-gplus-shareBrevet US6988237 - Error-correction memory architecture for testing production errors
Error-correction memory architecture for testing production errors
