A system and a method for reducing interrupt latency is described. The system includes a first interrupt source configured to generate a first interrupt, a second interrupt source configured to generate a second interrupt, and a processor. The processor includes a shadow set that stores data used to...http://www.google.fr/patents/US8135894?utm_source=gb-gplus-shareBrevet US8135894 - Methods and systems for reducing interrupt latency by using a dedicated bit
Methods and systems for reducing interrupt latency by using a dedicated bit
