A test circuit used for determining a fault in a memory device. The test circuit includes a read circuit configured to read memory cell contents in a memory device at a first time instant and second time instant. The test circuit includes a comparator that compares the contents at the first and second...http://www.google.fr/patents/US20070242538?utm_source=gb-gplus-shareBrevet US20070242538 - Apparatus and methods for determining memory device faults
Apparatus and methods for determining memory device faults
Numéro de demande: 11/404,667 Numéro de publication: US 2007/0242538 A1 Date de dépôt: 14 avr. 2006 Brevet délivré: US7548473 ( Date de délivrance 16 juin 2009)
