A data processing system comprised of a memory, a translation lookaside buffer (TLB) providing access to the memory, and an instruction cache connected to the memory. A two entry translation write buffer (TWB) has a first entry that is a first logical register and an associated first physical address...http://www.google.fr/patents/US5500948?utm_source=gb-gplus-shareBrevet US5500948 - Translating instruction pointer virtual addresses to physical addresses for accessing an instruction cache
Translating instruction pointer virtual addresses to physical addresses for ...
