A memory system using at least one DRAM chip and equipped with an interface for transferring input/output data in a packet format includes a plurality of banks within each of the at least one DRAM chip. The memory system further includes a control circuit for accessing a bank for data transfer of a given...http://www.google.fr/patents/US6055615?utm_source=gb-gplus-shareBrevet US6055615 - Pipeline memory access using DRAM with multiple independent banks
Pipeline memory access using DRAM with multiple independent banks
