A configurable logic block (CLB) having a plurality of identical configurable logic element CLE) slices is provided. Each CLE slice includes a plurality of function generators (lookup tables) that can be configured to form a random access memory (RAM). The width and depth of the RAM are selectable by...http://www.google.fr/patents/US6288568?utm_source=gb-gplus-shareBrevet US6288568 - FPGA architecture with deep look-up table RAMs
