By providing a hard mask layer stack including at least three different layers for patterning a gate electrode structure, constraints demanded by sophisticated lithography, as well as cap layer integrity, in a subsequent selective epitaxial growth process may be accomplished, thereby providing the potential...http://www.google.fr/patents/US7279389?utm_source=gb-gplus-shareBrevet US7279389 - Technique for forming a transistor having raised drain and source regions with a tri-layer hard mask for gate patterning
Technique for forming a transistor having raised drain and source regions ...
