An integrated circuit and fabrication method includes a vertical transistor for a memory cell in a dynamic random access memory (DRAM) or other integrated circuit. Vertically oriented access transistors are formed on semiconductor pillars on buried bit lines. Buried gates and body contacts are provided...http://www.google.fr/patents/US5909618?utm_source=gb-gplus-shareBrevet US5909618 - Method of making memory cell with vertical transistor and buried word and body lines
Method of making memory cell with vertical transistor and buried word and ...
