A memory array includes a first plurality of metal lines, a second plurality of diffusion bit lines and a third plurality of select transistors. There are more than two diffusion bit lines per metal bit line. The memory also includes a cell area formed of four segmented cell bit lines an even select...http://www.google.fr/patents/US6633496?utm_source=gb-gplus-shareBrevet US6633496 - Symmetric architecture for memory cells having widely spread metal bit lines
Symmetric architecture for memory cells having widely spread metal bit lines
