A synchronous bus system that enables the bus lengths between devices to be extended such that the timing budget is more than one clock cycle. A reset process resets the transmission and reception circuitry and both circuitry function according to prespecified parameters relative to the deassertion of...http://www.google.fr/patents/US6088370?utm_source=gb-gplus-shareBrevet US6088370 - Fast 16 bit, split transaction I/O bus
