An internal address signal corresponding to data to be written into a memory cell is held in a latch circuit. The held internal address signal is selected by a multiplexer in the next writing operation and applied to a decoder. Write data is taken in and held by the latch circuit during the period in...http://www.google.fr/patents/US5515325?utm_source=gb-gplus-shareBrevet US5515325 - Synchronous random access memory
